This invention relates to a circuit arrangement for processing sampled analogue electrical signals.
U.S. Pat. No. 4,864,217(9/15/89) and U.S. Pat. No. 4,866,368(9/12/89), the contents of which are hereby incorporated by reference, disclose a method of processing sampled analogue electrical signals in which the electrical quantity manipulated is current. This method is referred to hereinafter as switched current signal processing and circuit arrangements using this method are referred to as switched current circuits. It is known, in switched capacitor circuits, to manipulate electrical charges to perform signal processing of sampled analog electric signals. However, in order to manipulate the charges high quality linear capacitors are required and in MOS integrated circuits these are commonly fabricated using two polysilicon layers. The provision of two polysilicon layers is not a standard part of the CMOS processes usually used for LSI and VLSI digital circuits, which therefore makes the provision of circuits combining analog and digital signal processing on a single integrated circuit more difficult. In addition, the capacitors required for the signal manipulation in switched capacitor circuits occupy a large area which can be half or more of the total chip area. By using switched current circuits the processing and chip area problems may be mitigated. It has been found convenient to use current mirror circuits in the implementation of switched current circuits.
Current mirror circuits are well known in the art and have found uses in various applications. Generally a current mirror circuit comprises a pair of transistors where an input reference current source is connected to drive one of the transistors. The pair of transistors are connected together in a manner whereby the reference current is substantially reproduced or mirrored at the output of the second transistor. In most cases the critical factor in designing a current mirror circuit is providing optimum matching between the reference and output currents. U.S. Pat. No. 4,297,646 issued to LoCascio et al on Oct. 27th 1981 relates to a current mirror circuit comprising bipolar transistors with improved current matching provided by utilizing a single split collector lateral bipolar transistor.
Current mirrors can also be formed using MOS devices. One such arrangement is disclosed in U.S. Pat. No. 4,327,321 issued to H. Suzuki et al on Apr. 27th 1982. The Suzuki et al circuit also includes a resistor in the input rail between the p-channel MOSFET and an n-channel MOSFET to minimize the output current dependency on variations in the power supply voltage. The MOS technology small channel length devices are increasingly in demand. In relation to current mirror circuits the decrease in channel length results in a decrease of the output impendance of the current mirror. Cascoding techniques become necessary in order to increase the output impedance.
The advantages of cascoding transistors to form a stable current mirror circuit are further exemplified in U.S. Pat. No. 4,412,186 issued to K. Nagano on Oct. 25th 1983. Like the LoCascio arrangement, Nagano discloses a current mirror circuit comprising bipolar transistors. In the Nagano arrangement, however, the circuit includes two stages, each having three transistors of one conductivity type and a fourth of the opposite conductivity type. When the four transistors are matched the collector to emitter voltages VCE of the third and fourth transistors are equivalent to their base emitter voltages VDE.
One exemplary MOS circuit arrangement which utilizes cascoding is disclosed in U.S. Pat. No. 4,247,824 issued to R. A. Hilbourne on Jan. 27th 1981. This circuit maintains a high output impedance by utilizing a compensating voltage produced by the connection of an enhancement mode transistor in cascode with a depletion mode transistor.
These and other prior art cascode current mirror arrangements have not been widely used since they often exhibit one or more of the following problems: insufficient maximum voltage swing, excessive power consumption, insufficient output impedance, and inability to be incorporated into integrated circuit designs.
U.S. Pat. No. 4,583,037 claims to address the problem of providing a CMOS current mirror circuit which provides a high input voltage swing and accurate matching between input and output currents over a wide range of processing and temperature variations. However, the CMOS current mirror circuit disclosed in this U.S. Patent has a minimum input voltage of Vt+2Von where Vt is the threshold voltage and Von the turn-on voltage of the transistor.
A current mirror circuit arrangement comprising an input connected to an input branch of a first current mirror circuit, and an output connected to an output circuit branch of the first current mirror circuit wherein the input circuit branch comprises the series arrangement of first and second MOS transistors, the output circuit comprises the series arrangement of third and fourth MOS transistors with the gate electrodes of the first and third transistors connected together and to a bias source such that the first and third transistors are cascode connected, and with the gate electrodes of the third and fourth transistors connected together and to the input is disclosed in a paper entitled "A highly linear CMOS buffer amplifier" by John A. Fisher and Rudolph Koch published in IEEE Journal of Solid State Circuits, Vol. SC-22, No. 3, Jun. 1987, pages 330-334, in particular in FIGS. 1, 4 and 8. As can be seen from FIG. 8 of this paper, the cascode connected transistors M9 and M10 are biased by a fixed bias potential VB2. However, it has been found that, particularly when using source degeneration resistors, as the input current is reduced towards zero the voltage at the drain of transistor M9 approaches the threshold voltage V.sub.t and with a fixed bias potential VB2 transistor M9 can enter its linear region. Under these circumstances, in order to ensure saturation of transistor M9 at low input current levels, it is necessary to use low valued source degeneration resistors which results in poor degeneration and therefore in ineffective stabilisation of the matching, or to use large channel width to length (W/L) ratios which leads to large devices and the occupation of excessive chip areas.